UDSM CMOS Circuits

nur noch 3 lieferbar
  • Produktbeschreibung

    UDSM CMOS Circuits

    A simple and accurate delay model is proposed for Ultra Deep Sub-micron CMOS circuits (CMOS Inverter, NAND2, NOR2 etc) based on nth power law when the channel length is less than the 90nm. All the parameters are taken from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects i.e. Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), Substrate Current Induced Body Effect (SCBE), Drain-Induced Threshold Shift (DITS), which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 inputs CMOS NAND & NOR gates. Our result is better than simulation result with respect to both quality and estimation time. This work also thoroughly described the delay dependence on different parameters such as channel length, Load Capacitance, Supply voltage, Transition time, Velocity Saturation Coefficient, Threshold Voltage, Load Resistance, Width variation etc. This also explained the different power models for the estimation of UDSM circuts.
  • Zusatzinformation

    LAP Lambert Academic Publishing
    ISBN / EAN
  • Sie könnten auch an folgenden Produkten interessiert sein

    Art.Nr. 1028277

    Reiß:Praxisbuch IT-Dokumentation

    Art.Nr. 1479181

    Ramirez Molina:Diseño de una arquitectu

    Art.Nr. 1459513

    Seibert,J.:Anwend.v.Semantic-Web Techn.

  • 0 Kundenmeinungen

    Schreiben Sie selbst eine Rezension

    Ihre Meinung interessiert uns – und hilft anderen Kunden bei der Auswahl.